URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 242

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
242	Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set. Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior.	jshamlet	1538d 06h	/open8_urisc/trunk/VHDL/
241	Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation.	jshamlet	1543d 01h	/open8_urisc/trunk/VHDL/
240	Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal.	jshamlet	1545d 05h	/open8_urisc/trunk/VHDL/
231	Updated sample projects and added elapsed time capture (chronometer) module	jshamlet	1560d 09h	/open8_urisc/trunk/VHDL/
229	Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii.	jshamlet	1564d 06h	/open8_urisc/trunk/VHDL/
228	Added an initialization constant for the OPEN8_BUS_TYPE record.	jshamlet	1564d 20h	/open8_urisc/trunk/VHDL/
227	Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses.	jshamlet	1565d 03h	/open8_urisc/trunk/VHDL/
226	Forgot the updated package file...	jshamlet	1565d 07h	/open8_urisc/trunk/VHDL/
225	Added Halt_Ack to go with Halt_Req.	jshamlet	1565d 07h	/open8_urisc/trunk/VHDL/
224	Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals.	jshamlet	1565d 09h	/open8_urisc/trunk/VHDL/
223	Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up.	jshamlet	1566d 02h	/open8_urisc/trunk/VHDL/
222	Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator.	jshamlet	1566d 07h	/open8_urisc/trunk/VHDL/
221	o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more.	jshamlet	1567d 02h	/open8_urisc/trunk/VHDL/
220	More revision sections added	jshamlet	1567d 02h	/open8_urisc/trunk/VHDL/
219	Added revision block and corrected creation date.	jshamlet	1567d 02h	/open8_urisc/trunk/VHDL/
218	Revision sections added, vdsm8.vhd added.	jshamlet	1567d 02h	/open8_urisc/trunk/VHDL/
217	Broke out the vdsm8 as a separate entity, since it is used in several places, Even MORE code cleanup.	jshamlet	1567d 03h	/open8_urisc/trunk/VHDL/
216	Fixed missing parenthesis	jshamlet	1567d 05h	/open8_urisc/trunk/VHDL/
215	More code cleanup	jshamlet	1567d 05h	/open8_urisc/trunk/VHDL/
214	Initial add of some older code	jshamlet	1571d 03h	/open8_urisc/trunk/VHDL/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 242

Filtering Options