OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 282

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1259d 17h /open8_urisc/trunk/VHDL/
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1259d 20h /open8_urisc/trunk/VHDL/
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1259d 21h /open8_urisc/trunk/VHDL/
279 More comment cleanup jshamlet 1260d 18h /open8_urisc/trunk/VHDL/
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1261d 12h /open8_urisc/trunk/VHDL/
276 More comment fixes jshamlet 1296d 14h /open8_urisc/trunk/VHDL/
275 Fixed a minor comment error. jshamlet 1298d 08h /open8_urisc/trunk/VHDL/
274 Updated comments with more corrections jshamlet 1298d 15h /open8_urisc/trunk/VHDL/
273 Updated comments with corrections jshamlet 1298d 17h /open8_urisc/trunk/VHDL/
271 Removed deleted generic define. jshamlet 1308d 16h /open8_urisc/trunk/VHDL/
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.		 jshamlet 1308d 16h /open8_urisc/trunk/VHDL/
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1311d 06h /open8_urisc/trunk/VHDL/
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1311d 06h /open8_urisc/trunk/VHDL/
267 Corrected the file description to indicate this is an example package. jshamlet 1311d 07h /open8_urisc/trunk/VHDL/
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1311d 07h /open8_urisc/trunk/VHDL/
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1403d 15h /open8_urisc/trunk/VHDL/
264 Updated comments jshamlet 1413d 12h /open8_urisc/trunk/VHDL/
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.		 jshamlet 1413d 13h /open8_urisc/trunk/VHDL/
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1422d 16h /open8_urisc/trunk/VHDL/
261 Increased delay timer to 7 bits for button press detection. jshamlet 1429d 16h /open8_urisc/trunk/VHDL/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.