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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 283

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Rev Log message Author Age Path
283 Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. jshamlet 1260d 15h /open8_urisc/trunk/VHDL/
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1260d 15h /open8_urisc/trunk/VHDL/
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1260d 18h /open8_urisc/trunk/VHDL/
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1260d 19h /open8_urisc/trunk/VHDL/
279 More comment cleanup jshamlet 1261d 16h /open8_urisc/trunk/VHDL/
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1262d 10h /open8_urisc/trunk/VHDL/
276 More comment fixes jshamlet 1297d 12h /open8_urisc/trunk/VHDL/
275 Fixed a minor comment error. jshamlet 1299d 06h /open8_urisc/trunk/VHDL/
274 Updated comments with more corrections jshamlet 1299d 13h /open8_urisc/trunk/VHDL/
273 Updated comments with corrections jshamlet 1299d 15h /open8_urisc/trunk/VHDL/
271 Removed deleted generic define. jshamlet 1309d 15h /open8_urisc/trunk/VHDL/
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.		 jshamlet 1309d 15h /open8_urisc/trunk/VHDL/
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1312d 04h /open8_urisc/trunk/VHDL/
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1312d 05h /open8_urisc/trunk/VHDL/
267 Corrected the file description to indicate this is an example package. jshamlet 1312d 05h /open8_urisc/trunk/VHDL/
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1312d 05h /open8_urisc/trunk/VHDL/
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1404d 14h /open8_urisc/trunk/VHDL/
264 Updated comments jshamlet 1414d 11h /open8_urisc/trunk/VHDL/
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.		 jshamlet 1414d 11h /open8_urisc/trunk/VHDL/
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1423d 15h /open8_urisc/trunk/VHDL/

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