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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 289

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Rev Log message Author Age Path
289 Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. jshamlet 1147d 18h /open8_urisc/trunk/VHDL/
288 Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. jshamlet 1148d 14h /open8_urisc/trunk/VHDL/
287 Fixed mangled comments and revisioning dates. jshamlet 1149d 13h /open8_urisc/trunk/VHDL/
286 Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. jshamlet 1149d 14h /open8_urisc/trunk/VHDL/
285 Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. jshamlet 1156d 17h /open8_urisc/trunk/VHDL/
284 Corrected the vhdl unit name and description for o8_7seg.vhd jshamlet 1270d 04h /open8_urisc/trunk/VHDL/
283 Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. jshamlet 1273d 15h /open8_urisc/trunk/VHDL/
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1273d 16h /open8_urisc/trunk/VHDL/
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1273d 18h /open8_urisc/trunk/VHDL/
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1273d 19h /open8_urisc/trunk/VHDL/
279 More comment cleanup jshamlet 1274d 16h /open8_urisc/trunk/VHDL/
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1275d 10h /open8_urisc/trunk/VHDL/
276 More comment fixes jshamlet 1310d 13h /open8_urisc/trunk/VHDL/
275 Fixed a minor comment error. jshamlet 1312d 07h /open8_urisc/trunk/VHDL/
274 Updated comments with more corrections jshamlet 1312d 14h /open8_urisc/trunk/VHDL/
273 Updated comments with corrections jshamlet 1312d 15h /open8_urisc/trunk/VHDL/
271 Removed deleted generic define. jshamlet 1322d 15h /open8_urisc/trunk/VHDL/
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.		 jshamlet 1322d 15h /open8_urisc/trunk/VHDL/
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1325d 04h /open8_urisc/trunk/VHDL/
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1325d 05h /open8_urisc/trunk/VHDL/

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