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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 321

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Rev Log message Author Age Path
321 Fixed issue with parity flag in receiver sticking jshamlet 410d 21h /open8_urisc/trunk/VHDL/
320 Inverted flow control signals to match EIA-232 specification jshamlet 412d 23h /open8_urisc/trunk/VHDL/
319 Fixed off-by-one error in channel count jshamlet 414d 03h /open8_urisc/trunk/VHDL/
318 Added o8_scale_conv.vhd and intdiv.vhd jshamlet 418d 05h /open8_urisc/trunk/VHDL/
317 Altered the reinit signal on teh adc128s022.vhd driver to be optional, and removed the "dead" signal from the upper level o8_de0_nano_adc_if.vhd code. jshamlet 432d 01h /open8_urisc/trunk/VHDL/
316 More code cleanup and comments,
Removed INT_VECTOR_n constants, as they are superfluous. There are no reasonable situations in which the constants would be altered.		 jshamlet 432d 02h /open8_urisc/trunk/VHDL/
315 Added Terasic DE0 Nano ADC interface and rolling averager. jshamlet 432d 03h /open8_urisc/trunk/VHDL/
314 Code cleanup and added comments jshamlet 432d 04h /open8_urisc/trunk/VHDL/
313 Added all generics to package component jshamlet 432d 05h /open8_urisc/trunk/VHDL/
312 Added o8_timer24.vhd as a more flexible alternative to o8_sys_timer_ii.vhd.
Also cleaned up some comments in the HTML documentation		 jshamlet 432d 05h /open8_urisc/trunk/VHDL/
310 Added optional DACadv signal to advance the PWM engine using an external signal. This is used to synchronize the DAC with other DACs or for streaming multiple streams across a high-speed serial link. jshamlet 503d 07h /open8_urisc/trunk/VHDL/
308 jshamlet 524d 21h /open8_urisc/trunk/VHDL/
307 Fixed comments on o8_version.vhd jshamlet 732d 07h /open8_urisc/trunk/VHDL/
299 Modified the status_led.vhd to slow down the DIM50PCT signal to 1/32 instead of 1/2 for use with shift-register based discrete LEDs and added the ability to chain the toggle signal to save on resources as well as synchronize the "toggling" jshamlet 740d 18h /open8_urisc/trunk/VHDL/
298 Fixed a long-standing bug in the SBC instruction where the 1 wasn't being added to complete the 2's complement of Rn. This was causing off-by-one errors in subtraction and negating carry only subtractions. jshamlet 741d 21h /open8_urisc/trunk/VHDL/
297 Fixed register map comments jshamlet 1032d 05h /open8_urisc/trunk/VHDL/
296 Removed parallel interface from o8_vector_rx.vhd, modified vector_tx.vhd to use a generic for it's seed value, slight formatting change on o8_elapsed_usec.vhd. jshamlet 1040d 20h /open8_urisc/trunk/VHDL/
295 Undoing previous revision. UART was fine, bug reporter was not. jshamlet 1044d 00h /open8_urisc/trunk/VHDL/
294 Fixed an ancient bug in the parity logic that had the parity inverted. jshamlet 1044d 05h /open8_urisc/trunk/VHDL/
293 Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) jshamlet 1063d 05h /open8_urisc/trunk/VHDL/

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