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[/] [open_hitter/] [trunk/] [bench/] - Rev 22

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Rev Log message Author Age Path
22 mixed rising_edge / falling_edge logic removed stvhawes 3278d 00h /open_hitter/trunk/bench/
21 flakey sim bugs (1/10 test 2 fails) stvhawes 3278d 02h /open_hitter/trunk/bench/
20 search_control_sim prepped stvhawes 3284d 21h /open_hitter/trunk/bench/
19 search_control is up for simulation (ghdl) - tidied extra testbenches stvhawes 3291d 20h /open_hitter/trunk/bench/
18 search_control is up for simulation (ghdl) stvhawes 3291d 20h /open_hitter/trunk/bench/
17 persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id stvhawes 3297d 07h /open_hitter/trunk/bench/
16 minor fixes to search_control test bench stvhawes 3303d 18h /open_hitter/trunk/bench/
15 adding in search_control and testbench stvhawes 3304d 22h /open_hitter/trunk/bench/
14 search_item_wrapper bench debugged stvhawes 3310d 19h /open_hitter/trunk/bench/
13 test bench for search_item stvhawes 3313d 23h /open_hitter/trunk/bench/
12 wrapper test for search_item stvhawes 3319d 09h /open_hitter/trunk/bench/
10 split source files to sime and rtl stvhawes 3334d 00h /open_hitter/trunk/bench/
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3334d 23h /open_hitter/trunk/bench/
7 split clock/byte_ready and fix logic stvhawes 3339d 16h /open_hitter/trunk/bench/
6 fixing synthesizable stvhawes 3341d 01h /open_hitter/trunk/bench/
5 fixing synthesizable stvhawes 3341d 06h /open_hitter/trunk/bench/
3 developing ideas around unit test / fpga verification stvhawes 3341d 17h /open_hitter/trunk/bench/
2 initial sources, wrappers for regression test harness stvhawes 3352d 20h /open_hitter/trunk/bench/

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