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[/] [openarty/] - Rev 17

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17 Fixed the misaddressed I/O peripherals in the fastio peripheral group. In
particular, UART and GPS were misaddressed. This has now been fixed, so these
peripherals (should) match the spec. Further, the default speed of the two
UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the
GPS UART. The Aux UART transmitter also passes testing, so at least that one
works.		 dgisselq 2858d 09h /openarty/
16 This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects.		 dgisselq 2858d 10h /openarty/
15 These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed.		 dgisselq 2858d 11h /openarty/
14 All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test.		 dgisselq 2858d 11h /openarty/
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).		 dgisselq 2858d 11h /openarty/
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.		 dgisselq 2859d 14h /openarty/
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.		 dgisselq 2859d 14h /openarty/
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.		 dgisselq 2859d 14h /openarty/
9 Adding copywrite statement (oops). dgisselq 2859d 14h /openarty/
8 Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board.		 dgisselq 2859d 14h /openarty/
7 This implements the coordination of a massive build/test suite--just not the
actual configuration file itself.		 dgisselq 2859d 14h /openarty/
6 Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it.		 dgisselq 2859d 14h /openarty/
5 Initial checkin, this time of the bench testing s/w. dgisselq 2874d 17h /openarty/
4 Initial host software pack. dgisselq 2874d 17h /openarty/
3 Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet).		 dgisselq 2874d 17h /openarty/
2 Initial documentation/proposed specification. (I'm writing the spec as I'm
building the core.)		 dgisselq 2875d 12h /openarty/
1 The project and the structure was created root 2875d 16h /openarty/

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