URL https://opencores.org/ocsvn/openarty/openarty/trunk

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[/] [openarty/] - Rev 39

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Rev	Log message	Author	Age	Path
39	Fixes the OLED test so that it runs using the DMA.	dgisselq	2773d 00h	/openarty/
38	ZipLoad can now load programs to non-reset locations.	dgisselq	2773d 00h	/openarty/
37	Updated documentation and copyright.	dgisselq	2773d 00h	/openarty/
36	Lots of changes, see the git changelog for details.	dgisselq	2779d 09h	/openarty/
35	Added comments and copyright notice.	dgisselq	2782d 21h	/openarty/
34	These updates bring the distribution along to the point where both the GPS clock subsecond tracking, as well as the OLEDrgb controller now work.	dgisselq	2782d 23h	/openarty/
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	2788d 05h	/openarty/
32	Brought the CPU to its first working version, to include demo.	dgisselq	2789d 08h	/openarty/
31	Initial network is now working. Adding CPU control files to repository.	dgisselq	2790d 00h	/openarty/
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2790d 00h	/openarty/
29	Here's the memory pin list, necessary for running Xilinx's Memory Interface Generator.	dgisselq	2817d 21h	/openarty/
28	Including the updates and corrections from the wbuart32 project.	dgisselq	2817d 21h	/openarty/
27	Bus changes ...	dgisselq	2817d 21h	/openarty/
26	Adjusted the timing comments.	dgisselq	2817d 21h	/openarty/
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	2826d 05h	/openarty/
24	Here are the updates from the first (failed) attempt to try to integrate the DDR3 SDRAM controller onto this board.	dgisselq	2845d 01h	/openarty/
23	Includes settings necessary for the Arty to load from flash builds, and to reconfigure itself later.	dgisselq	2855d 00h	/openarty/
22	A useful script for programming the device, given that the current device program includes a valid comms interface.	dgisselq	2855d 00h	/openarty/
21	Removed the OLED controller one additional clock from the bus. This was necessary to maintain the 200MHz clock speed, especially given the growing fanout of the device bus.	dgisselq	2855d 00h	/openarty/
20	Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP mode turns it back off again, necessitating a new write to the VCon register. Further, XIP mode starts in extended SPI mode, and only transfers in QSPI mode for data. Finally, two new commands have been created: enabling the SPI memory reset, and actually resetting the SPI memory. In general, these are all better--as the EQSPI flash controller now works with these changes, whereby it didn't really work without them before.	dgisselq	2855d 00h	/openarty/

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Subversion Repositories openarty

[/] [openarty/] - Rev 39

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