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[/] [openarty/] [trunk/] - Rev 39

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39 Fixes the OLED test so that it runs using the DMA. dgisselq 2775d 22h /openarty/trunk/
38 ZipLoad can now load programs to non-reset locations. dgisselq 2775d 22h /openarty/trunk/
37 Updated documentation and copyright. dgisselq 2775d 22h /openarty/trunk/
36 Lots of changes, see the git changelog for details. dgisselq 2782d 07h /openarty/trunk/
35 Added comments and copyright notice. dgisselq 2785d 18h /openarty/trunk/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2785d 20h /openarty/trunk/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2791d 03h /openarty/trunk/
32 Brought the CPU to its first working version, to include demo. dgisselq 2792d 05h /openarty/trunk/
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2792d 22h /openarty/trunk/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2792d 22h /openarty/trunk/
29 Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator.		 dgisselq 2820d 19h /openarty/trunk/
28 Including the updates and corrections from the wbuart32 project. dgisselq 2820d 19h /openarty/trunk/
27 Bus changes ... dgisselq 2820d 19h /openarty/trunk/
26 Adjusted the timing comments. dgisselq 2820d 19h /openarty/trunk/
25 The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v.		 dgisselq 2829d 03h /openarty/trunk/
24 Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board.		 dgisselq 2847d 23h /openarty/trunk/
23 Includes settings necessary for the Arty to load from flash builds, and to
reconfigure itself later.		 dgisselq 2857d 22h /openarty/trunk/
22 A useful script for programming the device, given that the current device
program includes a valid comms interface.		 dgisselq 2857d 22h /openarty/trunk/
21 Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus.		 dgisselq 2857d 22h /openarty/trunk/
20 Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before.		 dgisselq 2857d 22h /openarty/trunk/

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