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[/] [openarty/] [trunk/] - Rev 47

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47 Updated. dgisselq 2781d 18h /openarty/trunk/
46 Sped the UART simulator back up to 1MBaud. dgisselq 2781d 18h /openarty/trunk/
45 Updated the flash, and the flash test bench, for Quad I/O read commands. dgisselq 2781d 18h /openarty/trunk/
44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.		 dgisselq 2781d 18h /openarty/trunk/
43 Cleaned up the CPU memory documentation. dgisselq 2781d 18h /openarty/trunk/
42 Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test.		 dgisselq 2781d 18h /openarty/trunk/
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2781d 18h /openarty/trunk/
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2781d 18h /openarty/trunk/
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2781d 18h /openarty/trunk/
38 ZipLoad can now load programs to non-reset locations. dgisselq 2781d 18h /openarty/trunk/
37 Updated documentation and copyright. dgisselq 2781d 18h /openarty/trunk/
36 Lots of changes, see the git changelog for details. dgisselq 2788d 03h /openarty/trunk/
35 Added comments and copyright notice. dgisselq 2791d 14h /openarty/trunk/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2791d 16h /openarty/trunk/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2796d 22h /openarty/trunk/
32 Brought the CPU to its first working version, to include demo. dgisselq 2798d 01h /openarty/trunk/
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2798d 18h /openarty/trunk/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2798d 18h /openarty/trunk/
29 Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator.		 dgisselq 2826d 14h /openarty/trunk/
28 Including the updates and corrections from the wbuart32 project. dgisselq 2826d 15h /openarty/trunk/

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