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[/] [openarty/] [trunk/] [bench/] - Rev 38

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36 Lots of changes, see the git changelog for details. dgisselq 2783d 03h /openarty/trunk/bench/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2786d 16h /openarty/trunk/bench/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2791d 22h /openarty/trunk/bench/
32 Brought the CPU to its first working version, to include demo. dgisselq 2793d 01h /openarty/trunk/bench/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2793d 18h /openarty/trunk/bench/
28 Including the updates and corrections from the wbuart32 project. dgisselq 2821d 15h /openarty/trunk/bench/
15 These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed.		 dgisselq 2860d 18h /openarty/trunk/bench/
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.		 dgisselq 2861d 21h /openarty/trunk/bench/
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.		 dgisselq 2861d 21h /openarty/trunk/bench/
9 Adding copywrite statement (oops). dgisselq 2861d 21h /openarty/trunk/bench/
8 Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board.		 dgisselq 2861d 21h /openarty/trunk/bench/
5 Initial checkin, this time of the bench testing s/w. dgisselq 2877d 01h /openarty/trunk/bench/

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