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[/] [openarty/] [trunk/] [bench/] - Rev 52

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Rev Log message Author Age Path
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.		 dgisselq 2747d 02h /openarty/trunk/bench/
47 Updated. dgisselq 2767d 06h /openarty/trunk/bench/
46 Sped the UART simulator back up to 1MBaud. dgisselq 2767d 06h /openarty/trunk/bench/
45 Updated the flash, and the flash test bench, for Quad I/O read commands. dgisselq 2767d 06h /openarty/trunk/bench/
36 Lots of changes, see the git changelog for details. dgisselq 2773d 15h /openarty/trunk/bench/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2777d 04h /openarty/trunk/bench/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2782d 11h /openarty/trunk/bench/
32 Brought the CPU to its first working version, to include demo. dgisselq 2783d 13h /openarty/trunk/bench/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2784d 06h /openarty/trunk/bench/
28 Including the updates and corrections from the wbuart32 project. dgisselq 2812d 03h /openarty/trunk/bench/
15 These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed.		 dgisselq 2851d 07h /openarty/trunk/bench/
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.		 dgisselq 2852d 10h /openarty/trunk/bench/
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.		 dgisselq 2852d 10h /openarty/trunk/bench/
9 Adding copywrite statement (oops). dgisselq 2852d 10h /openarty/trunk/bench/
8 Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board.		 dgisselq 2852d 10h /openarty/trunk/bench/
5 Initial checkin, this time of the bench testing s/w. dgisselq 2867d 13h /openarty/trunk/bench/

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