OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [sw/] [board/] - Rev 51

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.		 dgisselq 2747d 14h /openarty/trunk/sw/board/
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2767d 18h /openarty/trunk/sw/board/
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2767d 18h /openarty/trunk/sw/board/
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2767d 18h /openarty/trunk/sw/board/
36 Lots of changes, see the git changelog for details. dgisselq 2774d 03h /openarty/trunk/sw/board/
35 Added comments and copyright notice. dgisselq 2777d 14h /openarty/trunk/sw/board/
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2777d 16h /openarty/trunk/sw/board/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2782d 22h /openarty/trunk/sw/board/
32 Brought the CPU to its first working version, to include demo. dgisselq 2784d 01h /openarty/trunk/sw/board/
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2784d 18h /openarty/trunk/sw/board/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2784d 18h /openarty/trunk/sw/board/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.