URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [sw/] [host/] - Rev 31

Rev	Log message	Author	Age	Path
31	Initial network is now working. Adding CPU control files to repository.	dgisselq	2787d 14h	/openarty/trunk/sw/host/
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2787d 14h	/openarty/trunk/sw/host/
22	A useful script for programming the device, given that the current device program includes a valid comms interface.	dgisselq	2852d 14h	/openarty/trunk/sw/host/
18	The device can now program and configure itself, allowing bootstrap possibilities. `	dgisselq	2852d 15h	/openarty/trunk/sw/host/
16	This returns the scope to its original configuration, where the decode() function is not allowed to have any side effects.	dgisselq	2854d 14h	/openarty/trunk/sw/host/
14	All changes made as a part of getting the flash driver up and running. Today, it successfully programmed a configuration into the Arty via wbprogram, so ... that's been my last/best test.	dgisselq	2854d 15h	/openarty/trunk/sw/host/
6	Minor updates, mostly to support the development of the DDR3 SDRAM--such as creating addresses for the debugging scope used to figure out what's going on with it.	dgisselq	2855d 18h	/openarty/trunk/sw/host/
4	Initial host software pack.	dgisselq	2870d 22h	/openarty/trunk/sw/host/