OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] - Rev 122

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4628d 16h /openmsp430/
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4700d 16h /openmsp430/
120 update tools changelog... olivier.girard 4731d 23h /openmsp430/
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 4732d 00h /openmsp430/
118 Changelog update (move to modified BSD license). olivier.girard 4732d 17h /openmsp430/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4732d 17h /openmsp430/
116 Update documentation to reflect the latest core updates. olivier.girard 4748d 17h /openmsp430/
115 Add linker script example. olivier.girard 4757d 17h /openmsp430/
114 Improved the VerifyCPU_ID procedure. olivier.girard 4760d 16h /openmsp430/
113 Created ChangeLog files... olivier.girard 4761d 16h /openmsp430/
112 Modified comment. olivier.girard 4765d 16h /openmsp430/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4766d 16h /openmsp430/
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4767d 16h /openmsp430/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4821d 01h /openmsp430/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4822d 14h /openmsp430/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4822d 14h /openmsp430/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4822d 15h /openmsp430/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4837d 15h /openmsp430/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4841d 17h /openmsp430/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4842d 22h /openmsp430/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.