OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] - Rev 68

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 Update synthesis scripts with the hardware multiplier support. olivier.girard 5251d 12h /openmsp430/
67 Added 16x16 Hardware Multiplier. olivier.girard 5251d 12h /openmsp430/
66 The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code.		 olivier.girard 5251d 15h /openmsp430/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5262d 02h /openmsp430/
64 Add Actel synthesis environment for size and speed analysis. olivier.girard 5272d 11h /openmsp430/
63 Add Altera synthesis environment for size and speed analysis. olivier.girard 5272d 12h /openmsp430/
62 Add Xilinx synthesis environment for size&speed analysis. olivier.girard 5272d 14h /openmsp430/
61 Update openMSP430 rtl. olivier.girard 5283d 01h /openmsp430/
60 Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ).		 olivier.girard 5283d 02h /openmsp430/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5285d 00h /openmsp430/
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5285d 00h /openmsp430/
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5285d 01h /openmsp430/
56 Update Design Compiler Synthesis scripts. olivier.girard 5289d 07h /openmsp430/
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5290d 02h /openmsp430/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5290d 05h /openmsp430/
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5290d 05h /openmsp430/
52 Re-add pdf documentation. olivier.girard 5295d 01h /openmsp430/
51 Re-add open-office documentation. olivier.girard 5295d 01h /openmsp430/
50 Re-add html documentation. olivier.girard 5295d 01h /openmsp430/
49 Temporar documentation removal because of broken SVN update. olivier.girard 5295d 01h /openmsp430/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.