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123 update changelog... olivier.girard 4688d 18h /openmsp430/trunk/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4688d 18h /openmsp430/trunk/
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4760d 18h /openmsp430/trunk/
120 update tools changelog... olivier.girard 4792d 01h /openmsp430/trunk/
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 4792d 02h /openmsp430/trunk/
118 Changelog update (move to modified BSD license). olivier.girard 4792d 19h /openmsp430/trunk/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4792d 19h /openmsp430/trunk/
116 Update documentation to reflect the latest core updates. olivier.girard 4808d 19h /openmsp430/trunk/
115 Add linker script example. olivier.girard 4817d 18h /openmsp430/trunk/
114 Improved the VerifyCPU_ID procedure. olivier.girard 4820d 18h /openmsp430/trunk/
113 Created ChangeLog files... olivier.girard 4821d 18h /openmsp430/trunk/
112 Modified comment. olivier.girard 4825d 17h /openmsp430/trunk/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4826d 18h /openmsp430/trunk/
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4827d 18h /openmsp430/trunk/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4881d 02h /openmsp430/trunk/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4882d 15h /openmsp430/trunk/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4882d 15h /openmsp430/trunk/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4882d 16h /openmsp430/trunk/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4897d 17h /openmsp430/trunk/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4901d 18h /openmsp430/trunk/

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