OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] - Rev 127

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
127 update changelog... olivier.girard 4649d 18h /openmsp430/trunk/
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.		 olivier.girard 4649d 18h /openmsp430/trunk/
125 update changelog... olivier.girard 4663d 21h /openmsp430/trunk/
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.		 olivier.girard 4664d 08h /openmsp430/trunk/
123 update changelog... olivier.girard 4685d 19h /openmsp430/trunk/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4685d 19h /openmsp430/trunk/
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4757d 19h /openmsp430/trunk/
120 update tools changelog... olivier.girard 4789d 02h /openmsp430/trunk/
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 4789d 03h /openmsp430/trunk/
118 Changelog update (move to modified BSD license). olivier.girard 4789d 20h /openmsp430/trunk/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4789d 20h /openmsp430/trunk/
116 Update documentation to reflect the latest core updates. olivier.girard 4805d 20h /openmsp430/trunk/
115 Add linker script example. olivier.girard 4814d 20h /openmsp430/trunk/
114 Improved the VerifyCPU_ID procedure. olivier.girard 4817d 19h /openmsp430/trunk/
113 Created ChangeLog files... olivier.girard 4818d 20h /openmsp430/trunk/
112 Modified comment. olivier.girard 4822d 19h /openmsp430/trunk/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4823d 19h /openmsp430/trunk/
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4824d 19h /openmsp430/trunk/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4878d 04h /openmsp430/trunk/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4879d 17h /openmsp430/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.