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35 Update documentation to reflect the latest Verilog changes. olivier.girard 5320d 23h /openmsp430/trunk/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5321d 00h /openmsp430/trunk/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5321d 01h /openmsp430/trunk/
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5322d 21h /openmsp430/trunk/
31 Update documentation (new Altera FPGA project + diverse minor updates) olivier.girard 5322d 22h /openmsp430/trunk/
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5322d 22h /openmsp430/trunk/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5322d 23h /openmsp430/trunk/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5331d 07h /openmsp430/trunk/
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5331d 07h /openmsp430/trunk/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5331d 07h /openmsp430/trunk/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5421d 04h /openmsp430/trunk/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5421d 05h /openmsp430/trunk/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5442d 03h /openmsp430/trunk/
22 Updated some links in the HTML documentation. olivier.girard 5455d 00h /openmsp430/trunk/
21 added discussion group info olivier.girard 5467d 01h /openmsp430/trunk/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5467d 21h /openmsp430/trunk/
19 added SVN property for keywords olivier.girard 5467d 21h /openmsp430/trunk/
18 Updated headers with SVN info olivier.girard 5467d 22h /openmsp430/trunk/
17 Updated header with SVN info olivier.girard 5467d 22h /openmsp430/trunk/
16 Updated header with SVN info olivier.girard 5467d 22h /openmsp430/trunk/

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