OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] - Rev 104

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4861d 14h /openmsp430/trunk/core/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4862d 07h /openmsp430/trunk/core/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4862d 08h /openmsp430/trunk/core/
99 Small fix for CVER simulator support. olivier.girard 4866d 08h /openmsp430/trunk/core/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4866d 08h /openmsp430/trunk/core/
95 Update some test patterns for the additional simulator supports. olivier.girard 4870d 08h /openmsp430/trunk/core/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4870d 08h /openmsp430/trunk/core/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4874d 09h /openmsp430/trunk/core/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4897d 06h /openmsp430/trunk/core/
85 Diverse RTL cosmetic updates. olivier.girard 4897d 08h /openmsp430/trunk/core/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4902d 09h /openmsp430/trunk/core/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4951d 15h /openmsp430/trunk/core/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4963d 09h /openmsp430/trunk/core/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4968d 08h /openmsp430/trunk/core/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5050d 09h /openmsp430/trunk/core/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5075d 09h /openmsp430/trunk/core/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5077d 10h /openmsp430/trunk/core/
68 Update synthesis scripts with the hardware multiplier support. olivier.girard 5224d 17h /openmsp430/trunk/core/
67 Added 16x16 Hardware Multiplier. olivier.girard 5224d 17h /openmsp430/trunk/core/
66 The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code.		 olivier.girard 5224d 21h /openmsp430/trunk/core/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.