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[/] [openmsp430/] [trunk/] [core/] - Rev 59

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58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5278d 12h /openmsp430/trunk/core/
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5278d 12h /openmsp430/trunk/core/
56 Update Design Compiler Synthesis scripts. olivier.girard 5282d 18h /openmsp430/trunk/core/
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5283d 14h /openmsp430/trunk/core/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5283d 16h /openmsp430/trunk/core/
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5283d 16h /openmsp430/trunk/core/
37 olivier.girard 5312d 14h /openmsp430/trunk/core/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5312d 15h /openmsp430/trunk/core/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5312d 16h /openmsp430/trunk/core/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5433d 18h /openmsp430/trunk/core/
19 added SVN property for keywords olivier.girard 5459d 13h /openmsp430/trunk/core/
18 Updated headers with SVN info olivier.girard 5459d 13h /openmsp430/trunk/core/
17 Updated header with SVN info olivier.girard 5459d 13h /openmsp430/trunk/core/
6 Some more SVN ignore properties... olivier.girard 5481d 15h /openmsp430/trunk/core/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5494d 13h /openmsp430/trunk/core/

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