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[/] [openmsp430/] [trunk/] [core/] - Rev 80

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80 Create initial version of the Actel FPGA implementation example. olivier.girard 4959d 02h /openmsp430/trunk/core/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4970d 20h /openmsp430/trunk/core/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4975d 19h /openmsp430/trunk/core/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5057d 20h /openmsp430/trunk/core/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5082d 20h /openmsp430/trunk/core/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5084d 21h /openmsp430/trunk/core/
68 Update synthesis scripts with the hardware multiplier support. olivier.girard 5232d 04h /openmsp430/trunk/core/
67 Added 16x16 Hardware Multiplier. olivier.girard 5232d 04h /openmsp430/trunk/core/
66 The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code.		 olivier.girard 5232d 08h /openmsp430/trunk/core/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5242d 18h /openmsp430/trunk/core/
64 Add Actel synthesis environment for size and speed analysis. olivier.girard 5253d 04h /openmsp430/trunk/core/
63 Add Altera synthesis environment for size and speed analysis. olivier.girard 5253d 04h /openmsp430/trunk/core/
62 Add Xilinx synthesis environment for size&speed analysis. olivier.girard 5253d 06h /openmsp430/trunk/core/
60 Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ).		 olivier.girard 5263d 19h /openmsp430/trunk/core/
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5265d 17h /openmsp430/trunk/core/
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5265d 17h /openmsp430/trunk/core/
56 Update Design Compiler Synthesis scripts. olivier.girard 5270d 00h /openmsp430/trunk/core/
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5270d 19h /openmsp430/trunk/core/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5270d 21h /openmsp430/trunk/core/
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5270d 22h /openmsp430/trunk/core/

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