| Rev |
Log message |
Author |
Age |
Path |
| 192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3917d 17h |
/openmsp430/trunk/core/bench/verilog/ |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4345d 16h |
/openmsp430/trunk/core/bench/verilog/ |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4430d 15h |
/openmsp430/trunk/core/bench/verilog/ |
| 145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4483d 16h |
/openmsp430/trunk/core/bench/verilog/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4552d 16h |
/openmsp430/trunk/core/bench/verilog/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4859d 16h |
/openmsp430/trunk/core/bench/verilog/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4915d 15h |
/openmsp430/trunk/core/bench/verilog/ |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4935d 22h |
/openmsp430/trunk/core/bench/verilog/ |
| 99 |
Small fix for CVER simulator support. |
olivier.girard |
4940d 16h |
/openmsp430/trunk/core/bench/verilog/ |
| 98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4940d 17h |
/openmsp430/trunk/core/bench/verilog/ |
| 94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4944d 16h |
/openmsp430/trunk/core/bench/verilog/ |
| 84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
4976d 17h |
/openmsp430/trunk/core/bench/verilog/ |
| 76 |
Add possibility to simulate C code within the "core" environment. |
olivier.girard |
5042d 16h |
/openmsp430/trunk/core/bench/verilog/ |
| 72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5151d 18h |
/openmsp430/trunk/core/bench/verilog/ |
| 67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5299d 01h |
/openmsp430/trunk/core/bench/verilog/ |
| 65 |
Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. |
olivier.girard |
5309d 15h |
/openmsp430/trunk/core/bench/verilog/ |
| 54 |
Update FPGA projects with the combinatorial loop fixed. |
olivier.girard |
5337d 18h |
/openmsp430/trunk/core/bench/verilog/ |
| 34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5366d 18h |
/openmsp430/trunk/core/bench/verilog/ |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5366d 19h |
/openmsp430/trunk/core/bench/verilog/ |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5487d 20h |
/openmsp430/trunk/core/bench/verilog/ |
