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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] - Rev 99

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Rev Log message Author Age Path
99 Small fix for CVER simulator support. olivier.girard 4849d 06h /openmsp430/trunk/core/bench/verilog/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4849d 06h /openmsp430/trunk/core/bench/verilog/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4853d 05h /openmsp430/trunk/core/bench/verilog/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4885d 06h /openmsp430/trunk/core/bench/verilog/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4951d 05h /openmsp430/trunk/core/bench/verilog/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5060d 07h /openmsp430/trunk/core/bench/verilog/
67 Added 16x16 Hardware Multiplier. olivier.girard 5207d 14h /openmsp430/trunk/core/bench/verilog/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5218d 04h /openmsp430/trunk/core/bench/verilog/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5246d 08h /openmsp430/trunk/core/bench/verilog/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5275d 07h /openmsp430/trunk/core/bench/verilog/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5275d 08h /openmsp430/trunk/core/bench/verilog/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5396d 09h /openmsp430/trunk/core/bench/verilog/
17 Updated header with SVN info olivier.girard 5422d 05h /openmsp430/trunk/core/bench/verilog/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5457d 05h /openmsp430/trunk/core/bench/verilog/

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