| Rev |
Log message |
Author |
Age |
Path |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4971d 22h |
/openmsp430/trunk/core/rtl/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4986d 23h |
/openmsp430/trunk/core/rtl/ |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4992d 06h |
/openmsp430/trunk/core/rtl/ |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4992d 22h |
/openmsp430/trunk/core/rtl/ |
| 101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4993d 00h |
/openmsp430/trunk/core/rtl/ |
| 91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
5005d 01h |
/openmsp430/trunk/core/rtl/ |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
5027d 22h |
/openmsp430/trunk/core/rtl/ |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
5027d 23h |
/openmsp430/trunk/core/rtl/ |
| 84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
5033d 00h |
/openmsp430/trunk/core/rtl/ |
| 79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
5094d 01h |
/openmsp430/trunk/core/rtl/ |
| 74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5181d 01h |
/openmsp430/trunk/core/rtl/ |
| 72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5208d 02h |
/openmsp430/trunk/core/rtl/ |
| 67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5355d 08h |
/openmsp430/trunk/core/rtl/ |
| 66 |
The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code. |
olivier.girard |
5355d 12h |
/openmsp430/trunk/core/rtl/ |
| 60 |
Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ). |
olivier.girard |
5386d 23h |
/openmsp430/trunk/core/rtl/ |
| 57 |
Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file. |
olivier.girard |
5388d 22h |
/openmsp430/trunk/core/rtl/ |
| 53 |
Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)
Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch. |
olivier.girard |
5394d 02h |
/openmsp430/trunk/core/rtl/ |
| 34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5423d 01h |
/openmsp430/trunk/core/rtl/ |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5423d 02h |
/openmsp430/trunk/core/rtl/ |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5544d 04h |
/openmsp430/trunk/core/rtl/ |
