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[/] [openmsp430/] [trunk/] [core/] [rtl/] - Rev 166

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Rev Log message Author Age Path
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4265d 18h /openmsp430/trunk/core/rtl/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4350d 16h /openmsp430/trunk/core/rtl/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 4353d 18h /openmsp430/trunk/core/rtl/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4472d 18h /openmsp430/trunk/core/rtl/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4485d 18h /openmsp430/trunk/core/rtl/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4493d 17h /openmsp430/trunk/core/rtl/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4569d 18h /openmsp430/trunk/core/rtl/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4745d 19h /openmsp430/trunk/core/rtl/
112 Modified comment. olivier.girard 4778d 18h /openmsp430/trunk/core/rtl/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4779d 18h /openmsp430/trunk/core/rtl/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 4835d 17h /openmsp430/trunk/core/rtl/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 4850d 17h /openmsp430/trunk/core/rtl/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 4856d 00h /openmsp430/trunk/core/rtl/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+
olivier.girard 4856d 17h /openmsp430/trunk/core/rtl/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4856d 18h /openmsp430/trunk/core/rtl/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.
olivier.girard 4868d 19h /openmsp430/trunk/core/rtl/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4891d 16h /openmsp430/trunk/core/rtl/
85 Diverse RTL cosmetic updates. olivier.girard 4891d 18h /openmsp430/trunk/core/rtl/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.
olivier.girard 4896d 19h /openmsp430/trunk/core/rtl/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4957d 19h /openmsp430/trunk/core/rtl/

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