Rev |
Log message |
Author |
Age |
Path |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4959d 22h |
/openmsp430/trunk/core/rtl/verilog/ |
102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4960d 15h |
/openmsp430/trunk/core/rtl/verilog/ |
101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4960d 16h |
/openmsp430/trunk/core/rtl/verilog/ |
91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4972d 17h |
/openmsp430/trunk/core/rtl/verilog/ |
86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4995d 14h |
/openmsp430/trunk/core/rtl/verilog/ |
85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4995d 16h |
/openmsp430/trunk/core/rtl/verilog/ |
84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
5000d 17h |
/openmsp430/trunk/core/rtl/verilog/ |
79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
5061d 17h |
/openmsp430/trunk/core/rtl/verilog/ |
74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5148d 17h |
/openmsp430/trunk/core/rtl/verilog/ |
72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5175d 18h |
/openmsp430/trunk/core/rtl/verilog/ |
67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5323d 01h |
/openmsp430/trunk/core/rtl/verilog/ |
66 |
The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code. |
olivier.girard |
5323d 04h |
/openmsp430/trunk/core/rtl/verilog/ |
60 |
Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ). |
olivier.girard |
5354d 15h |
/openmsp430/trunk/core/rtl/verilog/ |
57 |
Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file. |
olivier.girard |
5356d 14h |
/openmsp430/trunk/core/rtl/verilog/ |
53 |
Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)
Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch. |
olivier.girard |
5361d 18h |
/openmsp430/trunk/core/rtl/verilog/ |
34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5390d 17h |
/openmsp430/trunk/core/rtl/verilog/ |
33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5390d 18h |
/openmsp430/trunk/core/rtl/verilog/ |
23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5511d 20h |
/openmsp430/trunk/core/rtl/verilog/ |
17 |
Updated header with SVN info |
olivier.girard |
5537d 15h |
/openmsp430/trunk/core/rtl/verilog/ |
2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5572d 15h |
/openmsp430/trunk/core/rtl/verilog/ |