Rev |
Log message |
Author |
Age |
Path |
180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4128d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4154d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
174 |
Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. |
olivier.girard |
4154d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4261d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4346d 08h |
/openmsp430/trunk/core/rtl/verilog/ |
149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4349d 10h |
/openmsp430/trunk/core/rtl/verilog/ |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4468d 10h |
/openmsp430/trunk/core/rtl/verilog/ |
132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4481d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
130 |
Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) |
olivier.girard |
4489d 08h |
/openmsp430/trunk/core/rtl/verilog/ |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4565d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4741d 11h |
/openmsp430/trunk/core/rtl/verilog/ |
112 |
Modified comment. |
olivier.girard |
4774d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4775d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4831d 08h |
/openmsp430/trunk/core/rtl/verilog/ |
105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4846d 09h |
/openmsp430/trunk/core/rtl/verilog/ |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4851d 15h |
/openmsp430/trunk/core/rtl/verilog/ |
102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4852d 08h |
/openmsp430/trunk/core/rtl/verilog/ |
101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4852d 10h |
/openmsp430/trunk/core/rtl/verilog/ |
91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4864d 10h |
/openmsp430/trunk/core/rtl/verilog/ |
86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4887d 07h |
/openmsp430/trunk/core/rtl/verilog/ |