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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 105

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Rev	Log message	Author	Age	Path
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4856d 11h	/openmsp430/trunk/core/sim/rtl_sim/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4861d 17h	/openmsp430/trunk/core/sim/rtl_sim/
102	Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH instructions are now working as expected: - indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 - indirect autoincrement: PUSH @R1+	olivier.girard	4862d 10h	/openmsp430/trunk/core/sim/rtl_sim/
101	Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source.	olivier.girard	4862d 11h	/openmsp430/trunk/core/sim/rtl_sim/
99	Small fix for CVER simulator support.	olivier.girard	4866d 11h	/openmsp430/trunk/core/sim/rtl_sim/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4866d 11h	/openmsp430/trunk/core/sim/rtl_sim/
95	Update some test patterns for the additional simulator supports.	olivier.girard	4870d 11h	/openmsp430/trunk/core/sim/rtl_sim/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4870d 11h	/openmsp430/trunk/core/sim/rtl_sim/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4874d 12h	/openmsp430/trunk/core/sim/rtl_sim/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4897d 09h	/openmsp430/trunk/core/sim/rtl_sim/
85	Diverse RTL cosmetic updates.	olivier.girard	4897d 11h	/openmsp430/trunk/core/sim/rtl_sim/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4951d 18h	/openmsp430/trunk/core/sim/rtl_sim/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4963d 12h	/openmsp430/trunk/core/sim/rtl_sim/
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4968d 11h	/openmsp430/trunk/core/sim/rtl_sim/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5050d 12h	/openmsp430/trunk/core/sim/rtl_sim/
73	Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh". This will prevent compatibility problems in systems where bash isn't the default shell.	olivier.girard	5075d 12h	/openmsp430/trunk/core/sim/rtl_sim/
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5077d 13h	/openmsp430/trunk/core/sim/rtl_sim/
67	Added 16x16 Hardware Multiplier.	olivier.girard	5224d 20h	/openmsp430/trunk/core/sim/rtl_sim/
65	Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1.	olivier.girard	5235d 10h	/openmsp430/trunk/core/sim/rtl_sim/
58	Update the debug hardware breakpoint verification patterns to reflect the latest design updates.	olivier.girard	5258d 09h	/openmsp430/trunk/core/sim/rtl_sim/

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 105

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