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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 63

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58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5240d 13h /openmsp430/trunk/core/sim/rtl_sim/
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5245d 15h /openmsp430/trunk/core/sim/rtl_sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5245d 18h /openmsp430/trunk/core/sim/rtl_sim/
37 olivier.girard 5274d 15h /openmsp430/trunk/core/sim/rtl_sim/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5274d 17h /openmsp430/trunk/core/sim/rtl_sim/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5274d 18h /openmsp430/trunk/core/sim/rtl_sim/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5395d 19h /openmsp430/trunk/core/sim/rtl_sim/
19 added SVN property for keywords olivier.girard 5421d 14h /openmsp430/trunk/core/sim/rtl_sim/
18 Updated headers with SVN info olivier.girard 5421d 14h /openmsp430/trunk/core/sim/rtl_sim/
17 Updated header with SVN info olivier.girard 5421d 15h /openmsp430/trunk/core/sim/rtl_sim/
6 Some more SVN ignore properties... olivier.girard 5443d 16h /openmsp430/trunk/core/sim/rtl_sim/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5456d 14h /openmsp430/trunk/core/sim/rtl_sim/

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