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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 94

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94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4912d 17h /openmsp430/trunk/core/sim/rtl_sim/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4916d 18h /openmsp430/trunk/core/sim/rtl_sim/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4939d 15h /openmsp430/trunk/core/sim/rtl_sim/
85 Diverse RTL cosmetic updates. olivier.girard 4939d 17h /openmsp430/trunk/core/sim/rtl_sim/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4994d 00h /openmsp430/trunk/core/sim/rtl_sim/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5005d 18h /openmsp430/trunk/core/sim/rtl_sim/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 5010d 17h /openmsp430/trunk/core/sim/rtl_sim/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5092d 18h /openmsp430/trunk/core/sim/rtl_sim/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5117d 18h /openmsp430/trunk/core/sim/rtl_sim/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5119d 19h /openmsp430/trunk/core/sim/rtl_sim/
67 Added 16x16 Hardware Multiplier. olivier.girard 5267d 02h /openmsp430/trunk/core/sim/rtl_sim/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5277d 16h /openmsp430/trunk/core/sim/rtl_sim/
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5300d 15h /openmsp430/trunk/core/sim/rtl_sim/
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5305d 16h /openmsp430/trunk/core/sim/rtl_sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5305d 19h /openmsp430/trunk/core/sim/rtl_sim/
37 olivier.girard 5334d 17h /openmsp430/trunk/core/sim/rtl_sim/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5334d 18h /openmsp430/trunk/core/sim/rtl_sim/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5334d 19h /openmsp430/trunk/core/sim/rtl_sim/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5455d 21h /openmsp430/trunk/core/sim/rtl_sim/
19 added SVN property for keywords olivier.girard 5481d 16h /openmsp430/trunk/core/sim/rtl_sim/

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