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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] - Rev 122

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122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4638d 14h /openmsp430/trunk/core/sim/rtl_sim/bin/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4776d 13h /openmsp430/trunk/core/sim/rtl_sim/bin/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4832d 12h /openmsp430/trunk/core/sim/rtl_sim/bin/
99 Small fix for CVER simulator support. olivier.girard 4857d 14h /openmsp430/trunk/core/sim/rtl_sim/bin/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4857d 14h /openmsp430/trunk/core/sim/rtl_sim/bin/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4861d 13h /openmsp430/trunk/core/sim/rtl_sim/bin/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4959d 13h /openmsp430/trunk/core/sim/rtl_sim/bin/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5066d 15h /openmsp430/trunk/core/sim/rtl_sim/bin/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5068d 15h /openmsp430/trunk/core/sim/rtl_sim/bin/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5226d 12h /openmsp430/trunk/core/sim/rtl_sim/bin/
37 olivier.girard 5283d 13h /openmsp430/trunk/core/sim/rtl_sim/bin/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5283d 16h /openmsp430/trunk/core/sim/rtl_sim/bin/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5404d 17h /openmsp430/trunk/core/sim/rtl_sim/bin/
17 Updated header with SVN info olivier.girard 5430d 13h /openmsp430/trunk/core/sim/rtl_sim/bin/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5465d 13h /openmsp430/trunk/core/sim/rtl_sim/bin/

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