| Rev |
Log message |
Author |
Age |
Path |
| 141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4424d 17h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4437d 04h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4468d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4565d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4637d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4775d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4831d 17h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 99 |
Small fix for CVER simulator support. |
olivier.girard |
4856d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4856d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4860d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 76 |
Add possibility to simulate C code within the "core" environment. |
olivier.girard |
4958d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 73 |
Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell. |
olivier.girard |
5065d 19h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5067d 20h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 65 |
Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. |
olivier.girard |
5225d 17h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 37 |
|
olivier.girard |
5282d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5282d 21h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5403d 22h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 17 |
Updated header with SVN info |
olivier.girard |
5429d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
| 2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5464d 17h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
