URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [run/] - Rev 55

Rev	Log message	Author	Age	Path
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5295d 00h	/openmsp430/trunk/core/sim/rtl_sim/run/
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5324d 00h	/openmsp430/trunk/core/sim/rtl_sim/run/
6	Some more SVN ignore properties...	olivier.girard	5492d 22h	/openmsp430/trunk/core/sim/rtl_sim/run/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5505d 21h	/openmsp430/trunk/core/sim/rtl_sim/run/