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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 99

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Rev Log message Author Age Path
95 Update some test patterns for the additional simulator supports. olivier.girard 4853d 11h /openmsp430/trunk/core/sim/rtl_sim/src/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4857d 12h /openmsp430/trunk/core/sim/rtl_sim/src/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4880d 09h /openmsp430/trunk/core/sim/rtl_sim/src/
85 Diverse RTL cosmetic updates. olivier.girard 4880d 11h /openmsp430/trunk/core/sim/rtl_sim/src/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4946d 12h /openmsp430/trunk/core/sim/rtl_sim/src/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5033d 12h /openmsp430/trunk/core/sim/rtl_sim/src/
67 Added 16x16 Hardware Multiplier. olivier.girard 5207d 20h /openmsp430/trunk/core/sim/rtl_sim/src/
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5241d 09h /openmsp430/trunk/core/sim/rtl_sim/src/
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5246d 11h /openmsp430/trunk/core/sim/rtl_sim/src/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5275d 13h /openmsp430/trunk/core/sim/rtl_sim/src/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5275d 13h /openmsp430/trunk/core/sim/rtl_sim/src/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5396d 15h /openmsp430/trunk/core/sim/rtl_sim/src/
19 added SVN property for keywords olivier.girard 5422d 10h /openmsp430/trunk/core/sim/rtl_sim/src/
18 Updated headers with SVN info olivier.girard 5422d 10h /openmsp430/trunk/core/sim/rtl_sim/src/
17 Updated header with SVN info olivier.girard 5422d 10h /openmsp430/trunk/core/sim/rtl_sim/src/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5457d 10h /openmsp430/trunk/core/sim/rtl_sim/src/

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