URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] - Rev 178

Rev	Log message	Author	Age	Path
178	Update all linker scripts with a simplified version. Thanks to Mihai M. for this one :-)	olivier.girard	4127d 21h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
145	Add Dhrystone and CoreMark benchmarks to the simulation environment.	olivier.girard	4389d 21h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
142	Beautify the linker script examples.	olivier.girard	4410d 22h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
141	Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later)	olivier.girard	4414d 21h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4458d 22h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4765d 22h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4932d 05h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4948d 22h	/openmsp430/trunk/core/sim/rtl_sim/src-c/