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[/] [openmsp430/] [trunk/] [fpga/] - Rev 149

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Rev	Log message	Author	Age	Path
149	Update simulation regression result parser. Fixed failing SFR test (due to newer MSPGCC version). Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)	olivier.girard	4334d 19h	/openmsp430/trunk/fpga/
143	Update FPGA software examples to support MSPGCC Uniarch.	olivier.girard	4405d 19h	/openmsp430/trunk/fpga/
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4422d 04h	/openmsp430/trunk/fpga/
136	Update all FPGA projects with the latest core version.	olivier.girard	4453d 18h	/openmsp430/trunk/fpga/
132	Update FPGA examples with the POP.B bug fix	olivier.girard	4466d 18h	/openmsp430/trunk/fpga/
128	Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 )	olivier.girard	4550d 18h	/openmsp430/trunk/fpga/
121	Add a new FPGA example for the LX9 Microboard from Avnet. Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)	olivier.girard	4694d 19h	/openmsp430/trunk/fpga/
112	Modified comment.	olivier.girard	4759d 18h	/openmsp430/trunk/fpga/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4760d 18h	/openmsp430/trunk/fpga/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4815d 03h	/openmsp430/trunk/fpga/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4816d 16h	/openmsp430/trunk/fpga/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4816d 16h	/openmsp430/trunk/fpga/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4816d 17h	/openmsp430/trunk/fpga/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4831d 18h	/openmsp430/trunk/fpga/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4835d 19h	/openmsp430/trunk/fpga/
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	4840d 18h	/openmsp430/trunk/fpga/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4841d 19h	/openmsp430/trunk/fpga/
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	4842d 19h	/openmsp430/trunk/fpga/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4845d 19h	/openmsp430/trunk/fpga/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4849d 19h	/openmsp430/trunk/fpga/

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[/] [openmsp430/] [trunk/] [fpga/] - Rev 149

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