OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] - Rev 54

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5373d 14h /openmsp430/trunk/fpga/
43 Re-add documentation (earlier pdf was broken). olivier.girard 5402d 11h /openmsp430/trunk/fpga/
42 olivier.girard 5402d 11h /openmsp430/trunk/fpga/
41 Update bitstream & SVN ignore patterns. olivier.girard 5402d 11h /openmsp430/trunk/fpga/
40 Minor updates. olivier.girard 5402d 11h /openmsp430/trunk/fpga/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5402d 11h /openmsp430/trunk/fpga/
38 Remove old core version. olivier.girard 5402d 12h /openmsp430/trunk/fpga/
37 olivier.girard 5402d 12h /openmsp430/trunk/fpga/
36 Remove old core version. olivier.girard 5402d 12h /openmsp430/trunk/fpga/
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5404d 11h /openmsp430/trunk/fpga/
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5404d 12h /openmsp430/trunk/fpga/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5404d 13h /openmsp430/trunk/fpga/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5412d 20h /openmsp430/trunk/fpga/
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5412d 20h /openmsp430/trunk/fpga/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5412d 21h /openmsp430/trunk/fpga/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5502d 18h /openmsp430/trunk/fpga/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5502d 18h /openmsp430/trunk/fpga/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5523d 16h /openmsp430/trunk/fpga/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5549d 11h /openmsp430/trunk/fpga/
16 Updated header with SVN info olivier.girard 5549d 12h /openmsp430/trunk/fpga/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.