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[/] [openmsp430/] [trunk/] [fpga/] - Rev 60

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59 Update the FPGA projects with the latest core design updates. olivier.girard 5368d 03h /openmsp430/trunk/fpga/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5373d 07h /openmsp430/trunk/fpga/
43 Re-add documentation (earlier pdf was broken). olivier.girard 5402d 03h /openmsp430/trunk/fpga/
42 olivier.girard 5402d 04h /openmsp430/trunk/fpga/
41 Update bitstream & SVN ignore patterns. olivier.girard 5402d 04h /openmsp430/trunk/fpga/
40 Minor updates. olivier.girard 5402d 04h /openmsp430/trunk/fpga/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5402d 04h /openmsp430/trunk/fpga/
38 Remove old core version. olivier.girard 5402d 05h /openmsp430/trunk/fpga/
37 olivier.girard 5402d 05h /openmsp430/trunk/fpga/
36 Remove old core version. olivier.girard 5402d 05h /openmsp430/trunk/fpga/
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5404d 04h /openmsp430/trunk/fpga/
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5404d 05h /openmsp430/trunk/fpga/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5404d 06h /openmsp430/trunk/fpga/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5412d 13h /openmsp430/trunk/fpga/
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5412d 13h /openmsp430/trunk/fpga/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5412d 13h /openmsp430/trunk/fpga/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5502d 11h /openmsp430/trunk/fpga/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5502d 11h /openmsp430/trunk/fpga/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5523d 09h /openmsp430/trunk/fpga/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5549d 03h /openmsp430/trunk/fpga/

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