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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [bench/] - Rev 221

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Rev Log message Author Age Path
221 Move old Altera-DE1 project to the OBSOLETE directory.
Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.		 olivier.girard 2911d 14h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4472d 16h /openmsp430/trunk/fpga/altera_de1_board/bench/
136 Update all FPGA projects with the latest core version. olivier.girard 4520d 15h /openmsp430/trunk/fpga/altera_de1_board/bench/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4827d 16h /openmsp430/trunk/fpga/altera_de1_board/bench/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4902d 16h /openmsp430/trunk/fpga/altera_de1_board/bench/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4908d 16h /openmsp430/trunk/fpga/altera_de1_board/bench/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4912d 16h /openmsp430/trunk/fpga/altera_de1_board/bench/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5334d 15h /openmsp430/trunk/fpga/altera_de1_board/bench/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5336d 16h /openmsp430/trunk/fpga/altera_de1_board/bench/

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