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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [sim/] - Rev 221

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Rev Log message Author Age Path
221 Move old Altera-DE1 project to the OBSOLETE directory.
Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.		 olivier.girard 2884d 19h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3159d 05h /openmsp430/trunk/fpga/altera_de1_board/sim/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4371d 18h /openmsp430/trunk/fpga/altera_de1_board/sim/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4462d 05h /openmsp430/trunk/fpga/altera_de1_board/sim/
136 Update all FPGA projects with the latest core version. olivier.girard 4493d 19h /openmsp430/trunk/fpga/altera_de1_board/sim/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4800d 20h /openmsp430/trunk/fpga/altera_de1_board/sim/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4856d 18h /openmsp430/trunk/fpga/altera_de1_board/sim/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4871d 19h /openmsp430/trunk/fpga/altera_de1_board/sim/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4881d 20h /openmsp430/trunk/fpga/altera_de1_board/sim/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4885d 20h /openmsp430/trunk/fpga/altera_de1_board/sim/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5090d 21h /openmsp430/trunk/fpga/altera_de1_board/sim/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5092d 21h /openmsp430/trunk/fpga/altera_de1_board/sim/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5239d 20h /openmsp430/trunk/fpga/altera_de1_board/sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5278d 22h /openmsp430/trunk/fpga/altera_de1_board/sim/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5307d 19h /openmsp430/trunk/fpga/altera_de1_board/sim/
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5309d 18h /openmsp430/trunk/fpga/altera_de1_board/sim/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5309d 20h /openmsp430/trunk/fpga/altera_de1_board/sim/

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