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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [synthesis/] - Rev 221

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Rev Log message Author Age Path
221 Move old Altera-DE1 project to the OBSOLETE directory.
Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.		 olivier.girard 2962d 19h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/synthesis/
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 4190d 21h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 4190d 21h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4364d 20h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
136 Update all FPGA projects with the latest core version. olivier.girard 4571d 20h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4878d 21h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4934d 19h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5317d 21h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
41 Update bitstream & SVN ignore patterns. olivier.girard 5385d 19h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
40 Minor updates. olivier.girard 5385d 20h /openmsp430/trunk/fpga/altera_de1_board/synthesis/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5387d 21h /openmsp430/trunk/fpga/altera_de1_board/synthesis/

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