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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] - Rev 109

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108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4855d 06h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4855d 06h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4870d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4874d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4880d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4884d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4888d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4911d 06h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
85 Diverse RTL cosmetic updates. olivier.girard 4911d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4916d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
83 Add Oscilloscope screenshot + link to the original game. olivier.girard 4962d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4962d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4965d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4965d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/

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