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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] - Rev 155

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4402d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4487d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4490d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4561d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4578d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
136 Update all FPGA projects with the latest core version. olivier.girard 4609d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4622d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4706d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
112 Modified comment. olivier.girard 4915d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4916d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4972d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4972d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4987d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4991d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4997d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 5001d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 5005d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 5028d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
85 Diverse RTL cosmetic updates. olivier.girard 5028d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 5033d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/

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