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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] - Rev 99

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Rev Log message Author Age Path
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4848d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4852d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4856d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4879d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
85 Diverse RTL cosmetic updates. olivier.girard 4879d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4884d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
83 Add Oscilloscope screenshot + link to the original game. olivier.girard 4930d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4930d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4933d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4933d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/

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