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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] - Rev 109

Rev	Log message	Author	Age	Path
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4892d 00h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4892d 00h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4911d 03h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4917d 02h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4921d 02h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5002d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/