URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] - Rev 107

Rev	Log message	Author	Age	Path
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4844d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4863d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4869d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4873d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4954d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/