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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 109

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107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4892d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4907d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4911d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4925d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4948d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
85 Diverse RTL cosmetic updates. olivier.girard 4948d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4953d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4999d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 5002d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5002d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/

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