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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 85

Rev	Log message	Author	Age	Path
85	Diverse RTL cosmetic updates.	olivier.girard	4904d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4909d 18h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4955d 18h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4958d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4959d 01h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/