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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 98

Rev	Log message	Author	Age	Path
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4985d 01h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	5007d 22h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
85	Diverse RTL cosmetic updates.	olivier.girard	5008d 00h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	5013d 01h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	5059d 01h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	5061d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5062d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/